Computer Architecture Lab

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This course is a hands-on introduction into computer architecture. The main target is to build a simple, pipelined microprocessor and run it in an FPGA. This course is associated with a real course at the Technical University of Denmark.

Martin Schoeberl

The Challenge[edit]

In this course you will design and develop extensions to the T-CREST time-predictable multicore processor and implement it in an FPGA.

The Rules[edit]

There are only two rules for your design:

  1. The design has to be pipelined
  2. The design has to run in an FPGA

Everything else is up to you. Be creative!

Additional Pages[edit]

  1. FPGA Hello World Example
  2. Summer 2015
  3. Projects
  4. HOWTO
  5. Processor Project


The lab work and the project are part of the final grade.

Following points are given for individual parts:

  • Instruction Set: 15 points
  • FPGA Design Flow: 15 points
  • Project design and implementation: 50 points
  • Project documentation (academic research paper style): 20 points


Several assignments will help you to get started. We will start on a weekly basis and loosen it up at the end when the main activity is designing your own processor.

As a first action add a template for your project and your name at the Student page.

Instruction Set[edit]

Find three different microprocessors and write a short summary (about 3 pages) about the instruction sets. Compare those three architectures.

Hint: describe simpler (older) architectures as found in processors for embedded systems.

Patmos Exercise[edit]

Explore Patmos with the provided VM.

Exercise document: Getting Started with Patmos

FPGA Design Flow[edit]

To get started using an FPGA start with following small projects:

A Simple Blinking LED

The FPGA Hello World Example describes the FPGA design flow with Quartus.

Explore Chisel with a Blinking LED

The very same example is available in Chisel: Chisel Hello World within folder hello-worls

UART Output

A UART will enable you to communicate between a PC and your processor. Therefore, this is our first real VHDL example. For this experiment, connect a serial cable between the FPGA board and the serial port on your PC. Start a terminal program (Hyperterm) with baud rate 115000 and no handshake.

Extend the blinking LED example with a UART and write 0 and 1 to the serial line when the LED is off and on.

The VHDL code for a UART is available here: sc_uart.vhd and fifo.vhd. The UART is connected via the SimpCon interface.

A Chisel version of the UART is available here: Uart.scala. The interface is a subset of OCP, described in the Patmos Reference Handbook.

With the slow output of characters (two per second) you can just write the data to the UART transmit register (offset 1).

Extend the example by writing repeated numbers 0-9 as fast as the baud rate allows. In this case you have to extend your state machine to poll the UART status register (at offset 0) to check if the transmit buffer is free.

UART Input (optional)

Implement a state machine that receives characters from the UART. Switch the LED on and off with two different commands received on the serial line.

ModelSim UART print out (optional, not with Chisel)

There is a faster simulation version of the UART available that prints the output to the ModelSim console: sim_sc_uart.vhd.

Having mastered this UART examples gives you a great tool to debug your processor design. The UART output will probably be the only way to communicate with your processor.

For further tips see HOWTO.

Argo NoC exercise[edit]

Argo NoC exercise

T-CREST Exploration[edit]

Get started with the T-CREST/Patmos project. See:


Either in a PDF file or (preferably) within Wikiversity.



To implement your design you can use any decent FPGA board. A serial interface (UART) will help for debugging. If you need more memory than the few KB on-chip the board should contain memory chips connected to the FPGA. I suggest using a board with SRAMs as they are easy to connect to the processor.


Add yourself to this list for this semester. It is strongly suggested for the students from DTU.

Summer 2016

The former student pages:

Summer 2015

Summer 2014

Summer 2013

Summer 2012

Summer 2011

Winter 2008

Winter 2007

Winter 2006

Summer 2006


TO DO[edit]

a short list of open issues:

  • nothing open at the moment