Computer Architecture Lab/SS2021
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Group 1
[edit | edit source]- Daniel Harringer 11775835
- Daniel Scheuchenstuhl 01630368
- Stefan Ulmer 11777750
Topic: Floating-Point Unit for Patmos
Group 2
[edit | edit source]- Daniel Zainzinger 11777778
- David Reitgruber 11777716
Topic: VGA controller
Group 3
[edit | edit source]- Dario Passarello s206639
- Lukáš Kyzlík s210229
- Tobias Rydberg s173899
Topic: 16-bit Pipelined Microprocessor Lyng
Notes:
- We defined our own ISA adapting ISA from this paper.
Group 4
[edit | edit source]- Lukas Stasytis s206670
Topic: Novel CORDIC accelerator using Xilinx FPGAs for solving Singular Value Decomposition
Group 5
[edit | edit source]- Szabolcs Garda s202472
- Bosse Bandowski s164582
Topic: Time-Predictable Neural Network Accelerator for the Patmos
Group 6
[edit | edit source]- Andreas Gamborg s163939
- William Wulff s174880
Topic: Argo NoC in Chisel
Group 7
[edit | edit source]- David Risom Pedersen s164872
- Casper Egholm Jørgensen s163950
- Tobias Frederik Flensberg Thomsen s152925
Topic: RSA accelerator
Group 8
[edit | edit source]- Jonas Ingerslev Sørensen s193274
- Felix Høgstædt Larsen s174296
- Andreas Holm Jørgensen s202743
Topic: 5 stage pipelined RISC-V microprocessor with dynamic branch prediction
Group 9
[edit | edit source]- Mikkel Aaslet s195129
Topic: 5 stage pipeline x32-BLAU
Group 10
[edit | edit source]- Edgars Kipans s144780
Topic: Roll Your Own Microprocessor - RISC-V (RVI32)