Computer Architecture Lab/SS2015

Group 1

Marek Dejak s136075

Bartek Gasior (s107181)

Group 2

Luca Pezzarossa s121273

Jesper Lønbæk s094726

Russell Barnes s146105

Jakob Toft s113012

Assignments

Instruction Set

Project

Design and implementation of an Ethernet connection, based on the UDP protocol, between the Patmos processor and a PC (or another Patmos processor) for the Terasic DE2-115 development board.

Group 3

Jens Joachim Krogsløkke Pedersen s103023

Thomas Onstrup Risager s103040

Stephan A. Nielsen s103035

Project: Roll-your-own CPU, based on a 16-bit RISC'ish architecture, with compact home made 16-bit instruction set.

Group 4

Joakim Sindholt s093442

Martin Wiingaard s103639

Daniel Kenji Pedersen s103636

Project Definition: Develop a NoC that uses distributed routing. Investigate the opportunity to remove the routing part of the header to enable a lager word pointer and increase the size of the payload in order to increase throughput.

Group 5

Alexandros Andreou, s145883

Linas Kaminskas, s082936

Mohamed Elmi, s146899

Our current ideas for a project will be one of the following:

Floating Point Unit (FPU) for Patmos.: While in general FPU's can consume a lot of power and processing time, performing DSP on embedded systems is still very useful and is performed in some scenarios. For example when one is working with a data collection systems that includes a multitude of sensors (ADC's, DAC's, actuators, accelerometers etc.) and one wants to do real-time processing. The goal is to implement an IEEE 784-2008 compliant FPU unit and instructions which the Patmos project can make use of. The IEEE 784-2008 standard can be found at IEEE Xplore Digital Library. The older standard IEEE 784-1985 can also be found at IEEE Xplore Digital Library. Further material at IEEE-754 Reference Material.
Direct Memory Access (DMA) for Patmos.: For a SoC or a modern computer architecture, Direct Memory Access (DMA) is undoubt one of the most useful features to have when moving data from peripherals to peripherals, memory to memory, or memory to peripherals (and vice versa). This reliefs the processing unit of performing tedious looping in order to copy or move data between two points. By having an arbitration mechanism or a secondary bus for data movement, and a fast implementation of a DMA unit, performance and power reductions can be gained, as parts of the main processing unit are not needed. With an interrupt mechanism, the processor can either go into a sleep state or continue by performing some other useful work. This project will concern the implementation of a simple DMA unit that is capable of moving data for the Patmos processor.

Assignmnet 1

Assignment Location

Group 6

Paulo Antonio Ferreira Da Silva Botelho, s146338

Christian Monrad Larsen, s097077

Géza Husi, s146146

Assignment 1

ISA comparison

Assignment 2

UART exercise

Project

NoC programmed in Chisel.
Details:
- Wormhole flow control
- XY routing
- Virtual Channels
- 4x4 mesh topology

Group 7

Christian Bering Bøgh, s952606

Assignments:

Instruction Set I.pdf
uart input and uart output exercises.

Project

Statically scheduled, 2-way superscalar CPU with flag stack and decomposed branches.