Computer Architecture Lab/SS2015/Group 2 - Assignment 1

Group 2
Luca Pezzarossa - s121273
Jesper Lønbæk - s094726
Russell Barnes - s146105
Jakob Toft - s113012

Assignment 1
In this report, we describe and compare the following three Instruction Set Architectures:

• Intel 4004
• VAX
• MIPS32

For each architecture, we provide a brief introduction, a description of the architecture and the specification, the instruction format, the addressing modes, and a brief discussion of the pros and cons. Finally, we compare the architectures with the help of a comparison table and list the references.

Intel 4004

Introduction

The Intel 4004 is one of the first developed general-purpose programmable microprocessors, and it was released by Intel in 1971. The 4004 was also the first microprocessor to be fully integrated into a single chip, which made it popular until 1978 when it was superseded by other microprocessors. The microprocessor Intel 4004 should not be confused with the MCS-4 chipset that is commonly referred to as 4004 because the Intel 4004 is the microprocessor of the MCS-4 chipset.

Architecture and specifications

The Intel 4004 is a 4-bit BCD-oriented microprocessor developed on 10µm technology, featuring a clock frequency of 740kHz. It is designed with a Complex Instruction Set Computing (CISC) accumulator architecture. The main specifications of the Intel 4004 are listed below:

• It is provided with 16 4-bit registers, capable of working in pairs to obtain 8-bit registers.
• It includes a 12-bit program counter and three 12-bit stack level registers, allowing 3-levels deep subroutine calls.
• The instruction set for the 4004 consists of 46 instructions, where each instruction is of either one or two bytes.

Instructions format

The 4004 instruction set consists of 46 instructions of either one or two bytes, making it a hybrid with regard to instruction length. Despite the low total amount of instructions, the instruction set is categorized as CISC due to the presence of load-operate instructions. The first byte is divided into two 4-bit fields, with the upper bits holding the opcode (operation code) and the lower bits holding the modifier. If it is a two byte instruction, the second byte contains address information or data. The instructions can at most take two operands. The different formats of the instructions can be observed in the following figures.

One byte instructions formats

opcode (4 bits)

index register address (4 bits)

opcode (4 bits)

index register pair address (4 bits)

opcode (4 bits)

data (4 bits)

Two bytes instructions formats

opcode (4 bits)

upper address (4 bits)

middle address (4 bits)

lower address (4 bits)

opcode (4 bits)

condition (4 bits)

middle address (4 bits)

lower address (4 bits)

opcode (4 bits)

index register address (4 bits)

middle address (4 bits)

lower address (4 bits)

opcode (4 bits)

index register pair address (4 bits)

upper data (4 bits)

lower data (4 bits)

Addressing modes

The 4004 instruction supports 6 different addressing modes: direct, indirect, immediate, same page, program RAM, and data RAM.

Discussion

The Intel 4004 is BCD-oriented because it was originally intended for calculation applications. Therefore, the processor is significantly different than most processors available today, as these are developed to use binary representation. The BCD-representation makes arithmetic operations more complex, on a hardware level, than they would be for binary representation. Additionally, storage is less dense using BCD, as 4 bits only represents 10 values instead of 16. On the other hand, with the BCD format, the arithmetic operations can be carried out more accurately, and it is easy to find the nth digit of a decimal number. The instruction set for the 4004 is of the CISC type, which makes it easier to develop software for the processor, as fewer instructions are needed.This may, however, reduce the achievable number of instructions per second.

VAX

Introduction and architecture

VAX is an acronym for Virtual Address Extension, and the instruction set architecture has been pointed out to be "the most successful minicomputer design in industry history. The machine is notable for being a favorite of hackers of its day. The VAX instruction set was developed by Digital Equipment Corporation (DEC) in 1977, which means it is from the same period as the MIPS instruction set, but with a very different design philosophy.

Architecture and specifications

The VAX architecture is a Complex Instruction Set Computing (CISC) memory-memory architecture. The main philosophies behind the VAX architecture and its main specifications are:

• The Instruction set is close to programming language in order to simplify compilers.
• The CISC approach minimizes the code size.
• It provides 16 General Pourpose Register (GPR) of 32 bits, and floating point arithmetic uses the same GPRs.
• The instructions are of variable length from 1 to 56 bytes and are briefly described in the following section.

Instructions format

The VAX instructions are of variable length from 1 to 56 bytes. The instructions begin with a single byte operation code (opcode) that contains the operation and the number of operands following the opcode. Each operand starts with a single byte that describes the addressing mode for that operand (address specifier). For example, for register addressing, this byte specifies the register number and the mode. In other cases, this initial byte can be followed by more bytes to specify the rest of the address information. The structure of the instructions is shown in the following figure.

opcode

operand 1

operand 2

-----

operand N

Addressing modes

The VAX architecture supports 10 different addressing modes: literal, immediate, register, register deferred, byte/word/long displacement, byte/word/long displacement deferred, indexed (scaled), autoincrement, autodecrement, and autoincrement deferred.

Discussion

The VAX philosophy led to a CISC architecture and a variable length instruction set. The CISC approach allows a direct usage of a rich language without the use of large and complex compilers. The variable length instruction set made the code more dense, which led to reduced memory usage. The two features, combined together, also made the architecture orthogonal (all the memory is accessible at any point in time). Some drawbacks of the implementation also result from the variable length of the instructions. The nature of the variable-length instructions leads to more clock cycles spent for the decoding of each opcode. The CISC architecture also seems difficult to extend and maintain backwards compatibility. The use of an orthogonal architecture also did not prove to be highly useful to engineers, since different studies showed that the usage of this feature was small.

MIPS32

Introduction

The MIPS32 (Microprocessor without Interlocked Pipeline Stages) architecture is a 32-bit Reduced Instruction Set Computing (RISC) architecture developed in 1981 by John L. Hennessy, professor at Stanford University and founder of the MIPS Technologies company. The MIPS architecture was and is currently used in many embedded systems (e.g. Cisco routers) and also gaming consoles (e.g., Nintendo 64, PS, PS2, PSP).

Architecture and specifications

The MIPS32 architecture is a register-register (load/store) architecture. Hence, the operands of the ALU can only come from the internal general purpose registers and not directly from memory (cache). Load and store operations can be used, respectively, to move data from the memory to the processor registers and vice versa. The main specifications of the MIPS32 architecture are listed below:

• The architecture uses a classic RISC pipeline, and it includes a single ALU for all the arithmetic and logic operations.
• MIPS32 provides 32 General Purpose Registers (GPR) of 32 bits each, some of which are reserved for special purposes (e.g., register $0 has a constant value of zero, register $31 is the return address for jumps and procedure calls, etc.).
• There are two special registers, HI and LO, used for multiplication and division results and accessible by the MFHI and MFLO instructions.
• It uses 32-bit fixed-length instructions, which are briefly described in the following section.

Instructions format

The MIPS32 architecture instructions are 32 bits long, and all of them belong to one of the following three different instruction types:

• R-type (Register): instructions that perform operations with three registers, such as arithmetic and logic operations (e.g., ADD, SUB, AND).
• I-type (Immediate): instructions that perform operations with two registers and an immediate operand, such as arithmetic and logic operations with constants, memory load/store operations and conditional branch (e.g., ADDI, XORI, LW, SW, BEQ, BNE).
• J-type (Jump): instructions that perform operations with only one immediate operand, such us the unconditional branch (e.g., J, JR).

The three different types are recognized by the value of the first 6 bits of the instruction (opcode), which also indicate how to interpret the remaining 26 bits of the instruction. The structures of the three types of instructions are shown in the following figure, where is possible to notice that the instruction fields are aligned.

R-type	op (6 bits)	rs (5 bits)	rt (5 bits)	rd (5 bits)	samt (5 bits)	funct (6 bits)
I-type	op (6 bits)	rs (5 bits)	rt (5 bits)	imm/addr (16 bits)
J-type	op (6 bits)	addr (26 bits)

In the figure, 'op' stands for opcode, 'rs' and 'rt' for source registers, 'rd' for destination register, 'samt' for shift amount, 'funct' for function, 'imm' for immediate operand, and 'addr' for address.

Addressing modes

The MIPS32 architecture supports 5 different addressing modes: register, immediate, base/displacement, PC-relative, and pseudo-direct.

Discussion

The MIPS32 RISC architecture reduces the complexity of the instructions, leading to a simplification in the hardware design and hence to an increase of the speed. Moreover, the MIPS architecture type (register-register) makes heavy usage of registers, a design that is very fast but increases the number of instructions required for complex operations with respect to the other approaches. Finally, the fixed length instructions approach allows a fast decoding and an easier design of the hardware implementation of the architecture. On the other hand, it introduces a bigger instruction memory usage and limitations in the instruction addressing space.

Comparison table

The following table compares the fundamental features of the 3 instruction set architectures presented above.

ISA	Intel 4004	VAX	MIPS32
Introduction year	1971	1977	1981
Bits	4 (BCD)	32	32
Architecture	Accumulator	Memory-memory	Register-register/load-store
Type	CISC	CISC	RISC
Registers number	16 (4 bits)	16 (32 bits)	32 (32 bits)
Max number of operators	2	6	3
Instructions length and encoding	1 or 2 bytes Hybrid	1 to 56 bytes Variable	32 bits Fixed
Instructions format	3 (1 byte instructions) 4 (2 bytes instructions)	-	3
Instructions number	46	123	68
Addressing modes	Direct Same page Indirect Immediate Program RAM Data RAM	Literal Immediate Register Register deferred Byte/word/long displacement Byte/word/long displacement deferred Indexed (scaled) Autoincrement Autodecrement Autoincrement deferred	Register Immediate Base/Displacement PC-relative Pseudo-direct

References

1. Intel 4004 Datasheet ([1])
2. Intel 4004 Architecture Accumulator ([2])
3. Intel 4004 Microprocessor Architecture ([3])
4. Intel 4004 Instructions Set ([4])
5. Wikipedia: Intel 4004 (Intel 4004)
6. Wikipedia: VAX (VAX)
7. VAX and Instruction Set Reference Manual ([5])
8. John L. Hennessy and David A. Patterson, Computer Architecture: A Quantitative Approach, Fourth Edition, Appendix B and J
9. MIPS32 Instruction Set Quick Reference ([6])
10. Wikipedia: MIPS Instruction Set (MIPS instruction set)
11. Wikipedia: List of Instruction Sets (List of instruction sets)