Computer Architecture Lab/WS2007

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Project page for the course in winter 2007.

Project FUBAR (Group 6)[edit]

Roland Kammerer, Christian Paukovits, Gernot Vormayr

µC comparison[edit]

(pdf version)

  • Altera NiosII
  • Atmel ATmega 16
  • Infineon C167
  • Motorola 68k

ISA and Assembler for the CPU[edit]

ISA: (pdf version)

Assembler: assembler (source code)

Simulator: simulator (source code)

CPU Documentation[edit]

pdf version

Project Nincompoop (Group 2)[edit]

Alexander Oh, Andreas Haschka, Claudia Hermann, Stefan Tauner

Instruction Set I[edit]

(pdf version)

  • Alpha
  • ARM
  • i960

Project MAD (Modern Auxilary Device) (Group 5)[edit]

Gerald Scharitzer, Markus Kammerstetter, Philipp Effenberger, Armin Novak

  • assignment 1
    • We have compared the following three ISAs (PDF):
   - Sparc
   - IBM S/360
   - Atmel AVR
  • assignment 3
    • The Quartus II projects for UART output and input are stored in our svn repository

Project LIAR - Liar Is A Risc (Group 3)[edit]

Michael Zöch, Michael Wessner, Gürsel Ayaz, Christoph Sieghart

Instruction Set I[edit]

Our analysis of three ISAs.

Instruction Set II[edit]

Our ISA and Assembler.

Project CZD (Group 4)[edit]

Eszter Csuta Manuel Zaera David Dobler

See Details here.

Assembler Source Code

Project -1 (Lucky .. das Ding aus dem See) (Group 7)[edit]

Bernhard Fischer, Hubert Kraut, Richard Salzer, Oliver Zendel

Instruction Set 1[edit]

For assignment Instruction Set 1 we examined the following processors:

   - MOS Technology 6502
   - Motorola 68k
   - ARM ARMv5

Instruction Set 2[edit]

The complete Instruction Set can be found in Instruction Set 2.

FPGA Design Flow[edit]

Our results can be found here: FPGA Design Flow.

Processor[edit]

Documentation of our processor.

Project Tante Emma (Group 1)[edit]

Alexandra Schuster, Franz Hartl, Harald Weillechner, Peter Hilber

Processor Comparison[edit]

Summary of the following microprocessors:

Instruction Set[edit]

We have a detailed description about our microprocessor, though some contents can change during development progress.

Assembler[edit]

To generate the binary input for the processor, download the actual version (v1.3) of our Tante Emma Assembler.

We generated some example assembler files which can be executed with the Tante Emma Assembler. We we have precompiled asm files, the binary files are also for download.

We further offer a short description for our assembler.

Simulation[edit]

We have generated a Matlab Simulation which includes all defined operations except division and multiplication. Furthermore the operations out, in, st, and ld are not implemented, since the data memory is not implemented. The instruction memory is only for test and therefore not exactly implemented as if it represents the RAM in real world. Branches, Jumps, returns and instruction cache misses are all tested and are working correct. You can download the actual version of our Tante Emma Simulator. To ran the simulation you need Matlab and Simulink.

Tante Emma Analysis[edit]

In this section we want to analyse our Tante Emma Processor in a more abstract way. We want to show features acourding to the Computer Architecture VO. For more details click here.

Project Διογένησ (Group 8)[edit]

Andreas Fellnhofer, David Rigler

Overview[edit]

  • Pipeline Schematic
  • Diogenes is a RISC Architecture CPU.
  • It has 4 pipeline stages, namely: Fetch, Decode, Execute and Writeback
  • Program and data-memory are separated (Harvard)
  • All instructions are 16 Bit wide
  • The general purpose registers and data-paths are 32-bit wide
  • No DRAM interface
  • Minimalistic design ==> high clock frequencies

Instruction Set I[edit]

   - MIPS I
   - ARM7
   - Z80

Comparison of these architectures: pdf

Instruction Set II[edit]

Tools[edit]

Examples[edit]

External Components[edit]

Downloads[edit]

VHDL Source, Assembler, Simulator and ASM Examples: tar.bz2

Project MoM (Group 9)[edit]

Florian Brandner

My project is somewhat special. I'm not writing a processor on my own, but instead write a tool that generates a VHDL model of the processors core from a high level specification. This high level architecture description language (ADL) is developed at the Christian Doppler Laboratory; and already used to generate a simulator model, and parts of a compiler from the same ADL model.

There is some (not much) information at my website: http://www.complang.tuwien.ac.at/cd/brandner

Overview[edit]

The core that is generated is based on the MIPS, as described in the book "Copmuter Organization & Design" by Hennessy and Patterson - with some modifications to get the "beast" running.

  • 4 stage pipeline
  • 32 32-bit general purpose registers
  • most integer instructions
  • pipeline, forwarding and control generated from the ADL model
  • hand coded instruction decoder, memory, I/O

Instruction Set[edit]

Most integer instructions are implemented - including all branch, load, store, logic and arithmetic operations.

Here are the most important limitations:

  • multiply: mult, multu
  • divide: div, divu
  • load: lwl, lwr (because of legal issues ;-)
  • store: swl, swr
  • all floating point and co-processor instructions
  • all privileged instructions
  • no exceptions (add, addiu, sub)

The list of instructions is available here: http://www.complang.tuwien.ac.at/cd/brandner/ca/mips.isa

Tools[edit]

Although many instructions are not available the regular MIPS tools (gcc, binutils, newlib) can be used - with some limitations of course.

You will need some additional files for newlib, these can be found here: http://www.complang.tuwien.ac.at/cd/brandner/ca/adllib.tar.bz2

Building the tools is an art on its own - a short how-to can be found here: http://www.jopwiki.com/MIPS

Examples[edit]

- Simple Hello World:

 #include <stdio.h>
 int main()
 {
   setbuf(stdout, NULL); /// disable buffering of I/O
   return puts("flo!\n");
 }

- Queens

 This program finds all the possible ways that N queens can
 be placed on an NxN chessboard so that the queens cannot
 capture one another.
 http://www.complang.tuwien.ac.at/cd/brandner/ca/queens.tar.bz2


Current Status[edit]

Currently everything works fine - after troubles synthesizing Block RAM with byte-enable. The example program is running on a Virtex-4 (XC4VL25) at 25Mhz. I'll try to get more examples running - but time is short :-)