Computer Architecture Lab/WS2007/Project -1 Lab3
This exercise was a prestep to designing and implementing our processor. The following tasks were implemented to get familiar with VHDL: -A simple blinking LED -simple UART output -extended UART output -UART input -[TODO]ModelSim UART print out
The only real pitfall was the extended UART task. We had to drive the supported UART code with its maximum transmission speed. To archive that we needed some way of recognizing that the previous data was send and that the UART was ready for the next value. Instead of using a simple signal line that goes up when the value is send (or something similar), this special UART uses the SimpleCon interface to mimic a separate information mode where two of the control flow bits are readable. This means we must switch to another address and read the UART input. Its LSB is the needed information bit.