Computer Architecture Lab/WS2007/diogenes external
Introduction[edit | edit source]
Diogenes has an 16 Bit wide external bus to connect (external) components. It could be 32Bit wide (like the registers), but none of the currently used components uses more than 16 Bit.
The external bus is accessed with the ldio and stio instructions. An address decoder uses the higher of the 16 bits address bits to distinguish between the different components.
We use the Spartan 3e Starter Kit.
LEDs[edit | edit source]
Address: 0000 0000 00xx xxxx
All writes with addresses that have 10 leading zeros go to the LEDs. Only the lower 8 Bits are used. The Leds are high active (1 means LED on) Reads to this addresses are unspecified.
Example access[edit | edit source]
ldi h0, 0 @ address of leds ldi h1, 0x81 @ bit pattern for outer LEDs on stio h1, [h0] @ write to LEDs
UART[edit | edit source]
Address: 0000 0000 10xx xxxx
The lower Bits of addresses with the above prefix, go directly to the UART module, however only addresses 0000 0000 1000 0000 and 0000 0000 1000 0001 are usable - one for the data- and one for the control register.
LCD[edit | edit source]
Address: 0000 0000 11YY xxxx
Writes with the prefix 0000 0000 11 are redirected to the LCD-controller chip of the spartan 3e board. Where YY specifies the used wires:
YY Values[edit | edit source]
00: RS @ select between data and controll register 01: RW @ read / write 10: E @ clock: must be explicitly handled in software 11: Data @ databits in 4 bitmode: bit7 - bit4
Example Access[edit | edit source]
ldi l0, 65 @ Letter 'A' ldi l1, 0xf0 @ DATA stio l0, [l1] ldi l1, 0xe0 @ E ldi l0, 0x1 stio l0, [l1] LDL h5, :wait_us call h5, <h5> ldi l1, 250 ldi l1, 0xe0 @ E ldi l0, 0x0 stio l0, [l1]
Program memory[edit | edit source]
Adress: 10xx xxxx xxxx xxxx
Writes that start with 10 are directed to the program memory. This is currently only used in the boot loader to load the user programs.
VGA[edit | edit source]
Adress: 11xx xxxx xxxx xxxx Writes that start with 11 are directed to the video ram.
The video memory is 8K (8192 Byte) large and is located in on chip memory (inside the FPGA). The video mode used by diogenes is 640x480Pixels with 8 (3Bit) colors per pixel. The pixel clock is 25MHz resulting in a refresh-rate of 60Hz. Using a linear video memory (like a frame buffer) would need at least 112KByte (640x480x3 = 921600Bit = 115200Byte) of memory, which is not available on the spartan chip. The use of off-chip memory would solve the problem, but we have chosen an other way around it.
The memory is logically organized as a matrix of 128 x 64 byte. The visible area of the screen is composed of 80x60 tiles each 8x8 Pixels in size. The larger part of the memory is used for tile numbers of the visible area (1Byte per index). The remaining memory is used to store the tile patterns. At most 96 different tiles can be simultaneously displayed on the screen, which is enough for some kind of text mode or simple graphics.