Computer Architecture Lab/WS2008/Group2/Documentation
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Members of Group 2, Sweet16
[edit | edit source]- Franz-Josef Katzdobler, 0425195
- Daniel Reichhard, 0025792
- Stefan Resch, 0425306
- Matthias Wenzl, 0425388
Instruction Set
[edit | edit source]Mnemonic | Operation | Opcode | Flags | ||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
NOP | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | C,Z | |
ADD | r1 := r1 + r2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | r2 | r1 | C,O,Z | |||||||
SUB | r1 := r1 - r2 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | r2 | r1 | C,O,Z | |||||||
MUL | r1 := r1 * r2 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | r2 | r1 | Z | |||||||
AND | r1 := r1 and r2 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | r2 | r1 | Z | |||||||
OR | r1 := r1 or r2 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | r2 | r1 | Z | |||||||
XOR | r1 := r1 xor r2 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | r2 | r1 | Z | |||||||
NOT | r1 := r1 not r2 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | r2 | r1 | Z | |||||||
SHL | r1 := r1 << r2 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | r2 | r1 | Z | |||||||
SHR | r1 := r1 >> r2 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | r2 | r1 | Z | |||||||
SLA | r1 := r1 << r2 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | r2 | r1 | O,Z | |||||||
SRA | r1 := r1 >> r2 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | r2 | r1 | Z | |||||||
MOV | r1 := r2 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | r2 | r1 | Z | |||||||
LD | r1 := mem(r2) | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | r2 | r1 | Z | |||||||
ST | mem(r1) := r2 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 0 | r2 | r1 | ||||||||
PUSH | stack(sp) := r1 , sp := sp + 1 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | r1 | |||||
POP | sp := sp - 1, r1 := stack(sp) | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 1 | r1 | Z | ||||
RETI | pc := intret | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | ||
FSR | r1 := status_register | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | r1 | |||||
JMP | pc := r1 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | r1 | |||||
CALL | reg15 := pc+1; pc := r1 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | r1 | |||||
RET | pc := r15 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
Assembler
[edit | edit source]The man page:
S16ASM(1) User Manuals S16ASM(1) NAME s16asm - sweet 16 assembler SYNOPSIS s16asm [-b | h | l | d | r] [-n][-o outfile ] [ infile ...] DESCRIPTION s16asm Transforms the given assembler source files to the selected des- tination format in the given order. If no infile is given, stdin will be used. The default destination format is raw. OPTIONS -b Output bytes in ASCII as binary number. -h Output bytes in ASCII as hex number in format of hexdump. -l Output as listing. -r Output as vhdl rom description. -d Output in format for bootloader. -n Supress warnings. -o outfile Place output to file outfile. Otherwise use stdout. BUGS Currently none know. Please send a mail when you find one. AUTHOR Stefan Resch Matthias Wenzl Daniel Reichhard Franz Katzdobler Sweet16 NOVEMBER 2008 S16ASM(1)
Assembler program for illustration:
//
// Short example for s16asm Assembler
//
// incrementing one number until it reaches 0xFCCF
// and enter endless loop afterwards
//
.org 0 // default orgin of first command is 0 anyway
.equ number r5
.equ start 64
.equ dest 0xFCCF
.org 0x0100
movi number, start
movi r6, >dest // Low Byte
movih r6, <dest // High Byte
.redo:
// calli memfun
mov r11, number // r11 ... first parameter register
calli increment
mov number, r0 // r0 ... first return register
sub r0, r6
brsnz redo // numbers not equal
.endless:
nop // nop is not necessary
jmpi endless // endless loop
//.org 20 // notice org directives must be higher than the previously
// written instruction
function increment (number1): // parameter number1 ... r11
mov out, number1
movi number1, >-1
movih number1, <-1 // don't forget the sign extension
sub out, number1 // use names for readability
ret
end function (out) // return register ... r0
function memfun:
push r5
pop r1
movi r1, 0
ld r2, r1
movi r2, 19
st r2, r5
ret
end function
High Level Simulator
[edit | edit source]Pipelining
[edit | edit source]The pipeline itself consists of 4 Stages:
- Fetch
- Decode
- Execute
- Memory Stage
You can see the functional description [here].
The interaction with the buttons, leds and all kinds of memories is managed by a memory interface unit. Following memory mapping is applied:
Memory | Begin | End | Comments | ||||||
---|---|---|---|---|---|---|---|---|---|
ROM | 0 | 0 | 0 | 0 | 0 | 0 | E | 0 | |
SPREGS | 0 | 0 | E | 1 | 0 | 0 | F | F | |
Program Space | 0 | 1 | 0 | 0 | F | F | F | F | |
UART ADDR | 0 | 0 | E | 1 | 0 | 0 | E | 1 | |
UART Read Data | 0 | 0 | E | 2 | 0 | 0 | E | 2 | |
UART Write Data | 0 | 0 | E | 3 | 0 | 0 | E | 3 | |
UART Control | 0 | 0 | E | 4 | 0 | 0 | E | 4 |