# Computer Architecture Lab/SS2014/group 5 lab 2

To model and implemented a CPU(Central Processing Unit) inside an FPGA, the CPU should be able to perform the task that of a normal CPU. The main processes are instruction fetch, instruction decode, memory read, execute and memory write back. Hence,CPU’s main function is to Fetch instructions, decode them and execute the given instruction set. Instruction set is based on MIPS.

Instruction set:

Instruction Function Encoding op funct
sub r1,r2,r3 subtraction: r1 <- r2 – r3 Register 000000 100010
mult r1,r2,r3 multiply: r1 <- r2 * r3 Register 000000 100100
div r1,r2,r3 division: r1 <- r2 / r3 Register 000000 100101
and r1,r2,r3 bitwise and: r1 <- r2 and r3 Register 000000 101000
or r1,r2,r3 bitwise or: r1 <- r2 or r3 Register 000000 101001
slt r1,r2,r3 set less than: r1 <- 1 if r2 < r3, r1 <- 0 otherwise Register 000000 110100
srl r1,r2,r3 shift from right to left: r1 <- r2 amount of r3 Register 000000 111000
slr r1,r2,r3 shift from left to right: r1 <- r2 amount of r3 Register 000000 111001
beq r1,r2,imm (destination) branch if equal r1 = r2: PC <- PC + imm × 4 Immediate 000010
jmp destination jump: PC <- PC + destination × 4 Jump 000001
lb r1,r2,imm load byte: r1 <- mem[r2 + imm] Immediate 100000
sb r1,r2,imm store byte: mem[r2 + imm] <- r1 Immediate 110000

Instruction format (32 bit):

Immediate:

6 bit 5 bit 5 bit 16 bit
op r1 r2 imm

Jump:

6 bit 26 bit
op destination

Register:

6 bit 5 bit 5 bit 5 bit 5 bit 6 bit
op r1 r2 r3 shift amount funct