The necessities in Digital Design

Number Systems

Binary Representation

Binary Numbers (A.pdf)
Hexadecimal Numbers (A.pdf)
Other Codes (A.pdf)

Binary Arithmetic

Binary Arithmetic (A.pdf)
BCD Arithmetic (A.pdf)

Interfacing Digital and Analog Signals

Sampling and Quantization (A.pdf)
Digital-to-Analog Conversion (A.pdf)
Analog-to-Digital Conversion (A.pdf)

C Program Examples

Binary Numbers in C programs (A.pdf)
Binary Addition in C programs (A.pdf)

Helpful Wikipedia Pages (C.pdf)

Floating Point Representations (5A.pdf)

See Floating Point Overview

See Offset Binary Overview

See Offset Binary & Sin / Cosine

See Offset Binary & ADC / DAC

Combinational Circuits

Analysis

Boolean Algebra (A1.pdf)
Truth Tables (A2.pdf)
K-Map (A3.pdf)
Design Examples (A4.pdf)

Components

Decoder (B1.pdf)
Encoder (B2.pdf)
Multiplexer (B3.pdf)
Adder (B4.pdf, fa.sch.pdf, adder4.sch.pdf)

Sequential Circuits

Analysis

Latches and Flipflops (A1.pdf)
State Transition Table (A2.pdf)
FSM (Finite State Machine) (A3.pdf)

Metastability (A4.pdf)
Flip-flop Timing (A5.pdf)
SR Latch Forbidden State (A6.pdf)
The Classic FF Design (A7.pdf)
The Modern FF Design (A8.pdf)

Components

Latches and Flip-flops (B1.pdf)
Registers (B2.pdf, register.pdf)
Counters (B3.pdf)

Array Devices

Memory Arrays

RAM
- RAM Structure (A.pdf)
- RAM Timing (B.pdf)
- FPGA RAM (C.pdf)

ROM

Logic Arrays

PLA
PAL
PLD
FPGA
- FPGA Structure
- FPGA Configuration (B.pdf)

Synchronous SRAM Timing
Asynchronous SRAM Timing
DRAM Timing

FPGA Architectures
CPLD & FPGA

RTL Design Techniques

Design Methodology

Synthesis

Logic Families and IOs

BJT Based

DTL (Diode-Transistor Logic)

TTL (Transistor-Transistor Logic)

ECL (Emitter-Coupled Logic)

MOS Based

CMOS (Complementary MOS)

Pseudo-nMOS

Transmission Gate

BiCMOS (Bipolr + CMOS)

Dynamic CMOS

Domino

Clocked-CMOS (C²MOS)

Modern I/O Standards

TTL and LVTTL (Low Voltage TTL)

CMOS and LVCMOS (Low Voltage CMOS)

SSTL (Stub Series Terminated Logic)

HSTL (High Speed Tranceiver Logic)

LVDS (Low Voltage Differential Signaling)

Wikipedia Pages for Logic Families (A.pdf)

go to [ Electrical_&_Computer_Engineering_Studies ]

Old

Until 2011.12 Chapter 1. Binary Numbers

1.1 Binary Numbers(pdf)

Minterm, Maxterm, HW

1.1 Lecture01(pdf)

Overflow HW

Overflow Table(pdf)

K-Map

K-Map(pdf)

Binary Adder

Binary Adder (C, S) (pdf)
Overflow detection circuit (V) (pdf)

BCD to Ex3 Code Coversion, Dont' Care

BCD to Ex3 Code Conversion (pdf)

Prime Implicant, Dont' Care

Prime Implicant, Don't Care (pdf)
HW 3.6 - explain the method of combining 0's and X's

Multiplexer / Demultiplexer

Multiplexer (pdf)
HW (TBD)

Flip Flop / Latch

FF & Latch (pdf)
FF & Latch HW (pdf)
Gated D Latch & Master-Slave D FlipFlop (pdf)
HW (Forbidden state and Indeterminate state) (pdf) (note in #2, S' R' instead of S R)
Classical Edge Triggered D FlipFlop (pdf)
HW (addition in SW and HW) (pdf)
FSM1 (pdf)
FSM2 (pdf)
HW (FSM Waveforms) (pdf)

Counter

Sychronous Counter (pdf)
Ripple Counter, Multiplexer, Tri-state buffer(pdf)
Register (pdf)
Timing (pdf)
HW (Multiplexer, Shift Register) (pdf)
Universal Shift Register, Memory Cell (pdf)
HW (Bit Serial Adder) (pdf)

Memory

Memory (pdf)

Comparator, Multiplier

Comparator, Multiplier (1.pdf, 2.pdf)

Multiplexer based design method

Multiplexer Design Method (1.pdf, 2.pdf)

midterm result (pdf)

Edge Triggered Flip Flop (pdf)
FF Timing (pdf)

Until 2013.07

Number Systems

Binary Numbers (A.pdf)
Hexadecimal Numbers (B.pdf)
Numbers in C programs (C.pdf)
Codes (pdf)

Helpful Wikipedia Pages (pdf)

Combinational Circuits

Truth Tables and Boolean Functions (2A.pdf)
K-Map (2B.pdf)
Binary Addition in C (2.C.pdf)
Binary Arithmetic (2.D.pdf)
Boolean Algebra (2.E.pdf)

Sequential Circuits

Latches and Flip-flops (3A.pdf)
FSM (Finite State Machine) (3B.pdf)
SR Latch Forbidden State (3C.pdf)
Flip-flop Timing (3D.pdf)
Metastability (3E.pdf)