Computer Architecture Lab/Winter2006/SHWH/Detailed description

Version 0.05

This version is also available as PDF.

Tante Emma - Processor Description

Instruction	Operation	Opcode	Flags	Description
ADD rA, rB	rA $\leftarrow$ rA + rB	0b000000	C,Z	Add without Carry
ADDC rA, rB	rA $\leftarrow$ rA + rB + C	0b100110	C,Z	Add with Carry
SUB rA, rB	Ra $\leftarrow$ rA - rB	0b000001	C,Z	Subtract without Carry
SUBC rA, rB	Ra $\leftarrow$ rA - rB - C	0b100111	C,Z	Subtract with Carry
AND rA, rB	rA $\leftarrow$ rA $\wedge$ rB	0b000010	Z	Logical AND
OR rA, rB	rA $\leftarrow$ rA $\vee$ rB	0b000011	Z	Logical OR
XOR rA, rB	rA $\leftarrow$ rA $\oplus$ rB	0b000100	Z	Exclusive OR
NEG rA	rA $\leftarrow$ 0x00 - rA	0b000101	Z,C	Two's Complement
INC rA	rA $\leftarrow$ rA + 1	0b000110	Z	Increment
DEC rA	rA $\leftarrow$ rA + 1	0b000111	Z	Decrement
CLR rA	rA $\leftarrow$ rA $\oplus$ rA	0b001000	Z	Clear register
SET rA	rA $\leftarrow$ 0xFF	0b001001	None	Set register
MUL rA, rB	r2:r1 $\leftarrow$ rA $\times$ rB	0b001010	Z,C	Multiply unsigned
DIV rA, rB	r2:r1 $\leftarrow$ rA / rB	0b001011	Z,C	Divide unsigned

Instruction	Operation	Opcode	Flags	Description
CALL	Stack $\leftarrow$ PC	0b001100	None	Call subroutine
JUMP	PC $\leftarrow$ Stack ??	0b001101	None	Jump
RET	PC $\leftarrow$ Stack	0b001110	None	Return from subroutine
CMP rA, rB	rA - rB	0b001111	Z,L,G	Compare
CMPSKIP rA, rB	if (rA == rB) PC $\leftarrow$ PC + 2	0b010000	None	Compare, skip if equal
BRZ	if (Z == 1) then PC $\leftarrow$ PC + Stack + 1	0b010001	None	Branch, if zero
BRNZ	if (Z == 0) then PC $\leftarrow$ PC + Stack + 1	0b010010	None	Branch, if not zero
BRL	if (L == 1) then PC $\leftarrow$ PC + Stack + 1	0b010011	None	Branch, if lower
BRNL	if (L == 0) then PC $\leftarrow$ PC + Stack + 1	0b010100	None	Branch, if not lower
BRG	if (G == 1) then PC $\leftarrow$ PC + Stack + 1	0b010101	None	Branch, if greater
BRNG	if (G == 0) then PC $\leftarrow$ PC + Stack + 1	0b010110	None	Branch, if not greater

Instruction	Operation	Opcode	Flags	Description
MOV rA, rB	rA $\leftarrow$ rB	0b010111	None	Copy Register
LDI rA, constant	rA $\leftarrow$ constant	0b011000	None	Load immediate
LD rA, rB	rA $\leftarrow$ (rB)	0b011001	None	Load
ST rA, rB	(rA) $\leftarrow$ rB	0b011010	None	Store
IN rA, PORT	rA $\leftarrow$ PORT	0b011011	None	In from I/O location
OUT rA, PORT	PORT $\leftarrow$ rA	0b011100	None	Out from I/O location
POP rA	rA $\leftarrow$ Stack	0b011101	None	Pop register from Stack; The Stack Pointer is pre-incremented by 1 before POP
PUSH rA	Stack $\leftarrow$ rA	0b011110	None	Push register on stack; The Stack Pointer is post-decremented by one after PUSH

Instruction	Operation	Opcode	Flags	Description
SHL rA	rA(n+1) $\leftarrow$ rA(n), rA(0) $\leftarrow$ 0, C $\leftarrow$ rA(7)	0b011111	Z,C	Logical shift left
SHR rA	rA(n) $\leftarrow$ rA(n+1), rA(7) $\leftarrow$ 0, C $\leftarrow$ rA(0)	0b100000	Z,C	Logical shift right
ASL rA	rA(n+1) $\leftarrow$ rA(n), n = 0,...,6	0b100001	Z,C	Arithmetic shift left
ASR rA	rA(n) $\leftarrow$ rA(n+1), n = 0,...,6	0b100010	Z,C	Arithmetic shift right
ROL rA	rA(0) $\leftarrow$ C, rA(n+1) $\leftarrow$ rA(n), C $\leftarrow$ rA(7)	0b100011	Z,C	Rotate left through Carry
ROR rA	rA(7) $\leftarrow$ C, rA(n) $\leftarrow$ rA(n+1), C $\leftarrow$ rA(0)	0b100100	Z,C	Rotate right through Carry

Instruction	Operation	Opcode	Flags	Description
NOP		0b100101	None	No Operation

Flag	Abbreviation	Default	Description
Zero	Z	0
Lesser	L	0
Greater	G	0
Carry	C	0

Bits	0-7	8-15	16-31
Content	Opcode	Register	Immediate or Unused

or

Bits	0-7	8-15	16-23	24-31
Content	Opcode	Register A	Register B	Unused

or

Bits	0-7	8-31
Content	Opcode	Unused

Our processor "Tante Emma" has 3 pipeline stages: