Computer Architecture Lab/Summer2006/CzinkPokornyResch/VRIPU
This is the project page for VRIPU (Very Reduced Instructions Processing Unit) microprocessor.
Short description[edit | edit source]
The goal of the VRIPU project is to design a pipelined RISC microprocessor which will only have a few instructions (about twenty).
VRIPU Datasheet[edit | edit source]
The datasheet for VRIPU can be found here.