# Computer Architecture Lab/SS2013/GROUP2 LAB2

## ISA

32-bit architecture, based on MIPS

### Registers

• 32 x 32-bit GPR name R0-R31, R0 always contains ‘0’, even if other value is stored in it.
• PC – Program Counter, inaccessible directly from assembler
• IF/ID, ID/EX, EX/MEM, MEM/WB – for pipeline, inaccessible from assembler (IF - instruction fetch, ID - instruction decode, EX - execute, MEM - memory access, WB - write back)
• AOL, AOH - registers that store 64-bit result of ALU operation (for 64-bit operands and 32- bit operands multiplication/division). AOL (states for Alu-Out-Low) contains lower 32 bits of result, AOH (Alu - Out - High) - higher 32 bits. (equivalent of LO and HI in MIPS!)

### General structure of instructions

#### ALU

##### 32-bit (ALU operands)
Rd = Rs (fuction) Rt
 Opcode (6) Rs (5) Rt (5) Rd (5) shift (5) Function (6)
##### 64-bit (ALU operands)
AOH AOL = (([Rs+1]<<32)+Rs) (function) (([Rt+1]<<32)+Rt)

Or, more formally:

AOL = ((([Rs+1]<<32)+Rs) (function) (([Rt+1]<<32)+Rt)) AND (232 -1)
AOH = ((([Rs+1]<<32)+Rs) (function) (([Rt+1]<<32)+Rt)) >> 32

Note: (Rs or Rt = 31 will be coupled with R0! It gives us simple way to add 64- and 32-bit numbers by putting 32-bit one in R31)
(It is some kind of Little Endian that simplifies implementation)

 Opcode(6) Rs (5) Rt (5) Shift (10) Function(6)
##### Immediate
Rd = Rs (function) Value
 Opcode (6) Rs (5) Rd (5) Value (16)

#### MEMORY

 Opcode (6) Rs (5) Rd (5) Offset (16)

#### CONTROL

##### Jump

 Opcode (6) Rs (5) Empty(21)
##### Branch
 Opcode (6) Rs (5) Rt (5) Value (16)

Value is signed

#### SPECIAL REGISTERS

 Opcode (6) Empty(5) Rd(5) Empty(16)