Computer Architecture Lab/SS2013/GROUP1 LAB1
The three ISA reviewed are Motorola DSP56000, ARM and Microchip PIC which is followed by a comparison.
Motorola DSP56000
[edit | edit source]The DSP56000, introduced in 1986, were the first microprocessor to implement the DSP56K ISA. The DSP56000 were mainly used for audio processing hence were able to perform fast multiplications and additions and also featured dual data-paths for parallel stereo audio processing. Due to its popularity a full C-Compiler has been released for architecture.
Features
[edit | edit source]- 24bit fixed instruction- and data-width.
- Local SRAM
- Harvard Architecture with One instruction- and two data-memories.
- Three stage pipeline (IF, ID, EX).
- 62 instruction mnemonics
Registers
[edit | edit source]- Two 24-bit registers for each path, that in "extended mode" could be concatenated to a single 48-bit register.
- 8 address Registers.
ALU
[edit | edit source]The ALU was implemented as a load / store architecture with the aforementioned registers. It also featured two 56-bit accumulators for fast (Single Cycle) Multiply-Accumulate (MAC) instructions.
Instruction Set
[edit | edit source]There are six types of instruction :
- Arithmetic
- Logical
- Bit Manipulative
- Loop
- Move
- Program Control
Many of these instruction are executed in dedicated units allowing for parallel execution, e.g. the Multiply-Accumulate can be executed while executing a parallel move on data in a single instruction cycle (2 clock cycles).
They are in general organized as follows :
Instructions format
| 23 DATA BUS MOVEMENT 8 | 7 OPCODE 0 |
|---|
Where the data bus movements can specify parallel moves from memory while executing the opcode. E.g. subtracting register Y from accumulator A and storing the result back in Y has the 8-bit opcode :
| 0 1 1 0 0 0 0 0 |
|---|
Where e.g. moving the contents of accumlator B into register X has the 16-bit code :
| 0 0 1 0 0 0 0 0 1 0 0 0 1 0 0 0 |
|---|
So to perform the subtraction and moving in parallel the instruction becomes :
| 0 0 1 0 0 0 0 0 1 0 0 0 1 0 0 0 | 0 1 1 0 0 0 0 0 |
|---|
Although not all instructions can be defined using just 8-bit, so these are extended into the data-bus segment and decoded accordingly. In total 30 of the 62 instroction mnemonics can execute the parallel data moves in a single instruction cycle. The remaining 32 either extend the instruction to 48-bit by considering the following instruction as an extension, or can simply not perform parallel data-movements while executing their instruction - which can be the case of e.g. bit-manipulative instructions that modifies data-words in memory, hence needs at most 24 bits for just specifying the memory address.
references
[edit | edit source]
ARM
[edit | edit source]The ARM is the most used 32-bit RISC architecture. One proof is that we can find it in almost all the modern mobile devices.
As RISC architecture, ARM adopt a uniform and fixed length of instruction fields to simplify instruction decode. Moreover, adopt a load/store architecture where data-processing operations only operate on register contents. It also adopts a simple addressing mode where all load/store addresses are determined from register contents and instruction fields only.
The ARM architecture add features to the basic RISC architecture that allow ARM processors to achieve a good balance of high performance, small code size, low power consumption, and small silicon area. Some of these features are the control over the Arithmetic Logic Unit (ALU) and shifter in most data-processing instructions, auto-increment and auto-decrement addressing modes to optimize program loops as well as conditional execution of almost all instructions to maximize execution throughput.
Registers
[edit | edit source]The ARM processor has a total of 37 registers which are divided into:
- 31 general-purpose registers.
- 6 status registers.
The visible registers for the programmer are:
- 15 general-purpose registers
- 2 status registers
- Program counter register
Instruction Set
[edit | edit source]The processor has to evaluate flags, before executing the instruction, to know if the instruction has to be executed or not. These flags are given by the Current Program Status Register (CSPR) and they are:
- zero (Z)
- carry / borrow / extend (C)
- overflow (V)
- negative / less than (N)
The ARM instruction set can be divided into six broad classes of instruction:
- Branch instructions.
- Data-processing instructions.
- Status register transfer instructions.
- Load and store instructions.
- Coprocessor instructions.
- Exception-generating instructions.
References
[edit | edit source]
MIcrochip PIC
[edit | edit source]The PIC (Peripheral Interface Controller) is a chip manufactured by Microchip Technology Inc., and it belongs to the Mid-range family of the microprocessor class.
The PIC consists of both a central processing unit and a memory which ranges from 1 to 4 kilobytes of words. The data memory reaches up to 256 bytes of EEPROM in the 16-series family.
It is a high-performance RISC CPU, with all 35, single cycle instructions except from branches, with an 8-level deep hardware stack for storing return addresses. It has separated code and data spaces which make it follow the Harvard Architecture and has one accumulator which use is implied. The program memory is addressed in 14-bit increments (bytes) the same as the instruction width in the mid-range families.
Registers
[edit | edit source]The data memory is partitioned into four banks which contain the General Purpose Registers (GPR) and the Special Function Registers (SFR). The Special Function Registers are located in the first 32 locations of each bank. The General Purpose Registers, implemented as static RAM, are located in the last 96 locations of each Bank.
Instruction Set
[edit | edit source]Each midrange instruction is a 14-bit word divided into an opcode which specifies the instruction type and one or more operands which further specify the operation of the instruction. The instruction set is grouped into three basic categories:
- Byte-oriented operations , with a further separation in Data Transfer instructions and Arithmetic-Logic instructions
- Bit–oriented operations
- Literal and control operations
All instructions are executed in one single instruction cycle, unless a conditional test is true or the program counter is changed as a result of an instruction. One instruction consists of four oscillator periods. Thus, for an oscillator frequency of 4 Mhz like in mid-range families the normal execution time is 1 μs.
References
[edit | edit source]
Comparison
[edit | edit source]The DSP56000 is based on CISC while the rest are based on RISC architecture.
Differences
[edit | edit source]| Motorola DSP56000 | ARM | Microchip PIC | |
| Number of Registers | 2 data reg + 8 address reg | 37 | 4 banks of register file |
| Register width | 24-bit | 32-bit | 8-bit |
| Pipeline stages | 3 | 3 up to 13 | 2 |
| Number of instructions | 62 | 36 | 35 |
| Type of Instructions | Arithmetic Logical Bit-manipulative Loop Move Program control |
Branch Data processing Status register transfer Load and store Coprocessor instruction Exception generation |
Byte-oriented Bit-oriented Literal and control operation |
Motolora DSP56000 is used mainly for audio processing in communication devices. ARM processor can be found in more than 90% of the smart phones today. Microchip PIC is widely used in industrial applications and hobbyist projects as it is inexpensive and comes with an extensive collection of application notes.