Understanding FPGA Design

From Wikiversity
Jump to navigation Jump to search

Programmable Logic Devices[edit]

  • PLA
  • PAL
  • GAL
  • CPLD
  • FPGA

FPGA Architectures[edit]

  • Basic structure of FPGAs (pdf)
  • FPGA based on SRAMs (pdf)
  • FPGA based on ROMs with anti-fuses (pdf)
  • FPGA based on Non-volatile Memories (pdf)
  • Features of FPGAs

Circuit Level Characteristics[edit]

  • Logic Cell Circuit
  • IO Cell Circuit
  • Interconnect Circuit

FPGA Development Phases[edit]

  • Design
  • Simulation
  • Synthesis
  • Implementation (pdf)
  • Programming

Clocking Scheme[edit]

  • Clock Control
  • Clock Domain
  • Reset Signals


  • Xilinx DCM & 2-phase clock, Contraining technique
  • Xilinx XPower, Power and Energy Aware Design?

Using ROM[edit]

  • VHDL Example Code ( pdf )


Latch based design[edit]

  • Latch in FGPA ( pdf )

Dual Edge Triggered Flip Flop based design[edit]


go to [ Electrical_&_Computer_Engineering_Studies ]