UTPA STEM/CBI Courses/Computer Architecture/CPU Design
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Course Title: Computer Architecture
Lecture Topic: CPU Design
Instructor: Yang Liu
Institution: University of Texas-Pan American
Backwards Design
[edit | edit source]Course Objectives
- Primary Objectives- By the next class period students will be able to:
- Design a simple CPU to execute instructions
- Sub Objectives- The objectives will require that students be able to:
- Operate various components such as register files, memory, ALU, control, etc.
- Implmenet data path and control path
- Difficulties- Students may have difficulty:
- Interaction between data path and control path
- Timing among different components
- Real-World Contexts- There are many ways that students can use this material in the real-world, such as:
- CPU design engieer on Linkedin: http://www.linkedin.com/title/cpu+design+engineer/
- Apple to expand CPU design group beyond iPad A4: http://www.appleinsider.com/articles/10/12/31/apple_to_expand_cpu_design_group_beyond_ipad_a4.html
- News on NVIDIA' project of high performance CPU: http://www.anandtech.com/show/4099/nvidias-project-denver-nv-designed-high-performance-arm-core
- Design and construction of simple CPU: http://cpuville.com/design.htm
Model of Knowledge
- Concept Map
- Data path
- Register file
- ALU
- memory
- Control path
- Control
- ALU control
- Execution of instruction
- Data path
- Content Priorities
- Enduring Understanding
- CPU needs both data path and control path to execute instructions***
- Important to Do and Know
- issues for actual circuit implementation such as clocking methodology
- Worth Being Familiar with
- Much more complications in real word product CPU
- Relationship between CPU design and instruction set
- Enduring Understanding
Assessment of Learning
- Formative Assessment
- In Class (groups)
- Exercise on how each component works
- Exercise on how an instruction is executed on the data path and control path
- Homework (individual)
- calcuate the critical path for given delays of components
- In Class (groups)
- Summative Assessment
- Write a simulator of a simple CPU
Legacy Cycle
[edit | edit source]OBJECTIVE By the next class period, students will be able to:
- Design a simple CPU to execute instructions
The objectives will require that students be able to:
- Operate various components such as register files, memory, ALU, control, etc.
- Implmenet data path and control path
THE CHALLENGE
IPAD is a sucessful product of Apple. Apple decides to hire new engineers to design a new CPU for next generation of IPAD. You are hired after your graduation. Show the link to the news on Apple: http://www.appleinsider.com/articles/10/12/31/apple_to_expand_cpu_design_group_beyond_ipad_a4.html
How do you design a CPU for that purpose?
GENERATE IDEAS
- Students discuss in pair what are needed inside a CPU
- Students talk about the tools needed to design CPU if they know any
MULTIPLE PERSPECTIVES
- Show the link to design and construction of simple CPU: http://cpuville.com/design.htm
- Show the link to Application-Customized CPU: http://www.ibm.com/developerworks/power/library/pa-fpfxbox/?ca=dgr-lnxw07XBoxDesign
RESEARCH & REVISE
- Students should know there are various components inside a CPU
- Students discuss how to use various components in a CPU
- Lectures on data path and control path is given
- Students search more information from Internet on CPU
TEST YOUR METTLE
- In-class exercises.
GO PUBLIC
- Complete the simulator project
Pre-Lesson Quiz
[edit | edit source]- CPU only needs to read, process, and write data. Is this claim correct or not? Why or why not?
Test Your Mettle Quiz
[edit | edit source]- Assume register i holds integer value i. (a) if rr1=5, rr2=12, wr=6, wd=-1, and regWrite=0, what happens after accessing the register file(including output and any other changes)? (b) if rr1=5, rr2=12, wr=6, wd=-1, and regWrite=1, what happens after accessing the register file(including output and any other changes)? (c) if rr1=5, rr2=12, wr=5, wd=-1, and regWrite=0, what happens after accessing the register file(including output and any other changes)?
- (a) What does regDst=1 and regWrite=1 mean for R-format instructions? (b) Why are ALUsrc=1, memToReg=1, regWrite=1 and memRead=1 for lw instruciton? (c) Why do the values of regDst and memToReg not matter for beq instruction?
- Show the execution and critical path of instruction "add $s0, $s1, $s2" with given component delays.