Understanding VLSI Design

CMOS VLSI Design

• Introduction (pdf)

Design Objects

Device

• MOSFET-1 : Capacitors (pdf)
• MOSFET-2 : Operation Modes (pdf)
• MOSFET-3 : Capacitance Types (pdf)
• MOSFET-4 : Body Effect, Latchup (pdf)
• MOSFET-5 : Energy Band Diagrams (pdf)
• (Energy Band)

• Inverter-1 : Inverter, VTC, Noise Margin (pdf)
• Inverter-2 : nMOS Linear Model, nMOS Resistance, nMOS Capacitance (pdf)
• Inverter-3 : Inverter Fall Delay & Rise Delay, Propagation Delay, and Gate Delay (pdf)

• PassTr : Pass Transistor (pdf)

Design Tools

Spice Model & Simulation

• Spice (pdf)

Layout & Simulation

• Electric (Static Free Software)
• LT Spice (Linear Technology)

Design Constraints

Delay

Logic Level Delay Overview

• Background (pdf)
• RTL Timing (pdf)
• Delay Models in Verilog (pdf)
• Delay Annotation and SDF (pdf)

See Timing Characterization

CMOS Level Delay

• Delay-1 : Transistor Sizing (pdf)
• Delay-2 : Logical Effort (pdf)
• Delay-3 : Logical Effort Applications (pdf)
• Delay-4 : Device Delay (pdf)
• Delay-5 : Inverter Chain Delay (pdf)
• Delay-6 : Multistage Delay (pdf)
• Delay-7 : Elmore Delay (pdf)
• Delay-8 : Delay Model (pdf)
• Delay-9 : Wire Delay (pdf)
• Delay-A : Logical Effort and Gate Sizing

Power

Logic Level Power Overview

CMOS Level Power

• Power-1 (pdf) : Power

Design Techniques

Simple Logic Gate Design

NAND Gate Design

• NAND (pdf)

NOR Gate Design

• NOR (pdf)

Combinational Circuit Design

Logic Level Combinational Circuit Design Overview

• Background (pdf)

CMOS Level Combinational Circuit Design

• Combinational-1 : Pull Up Network, Pull Down Network, AOI, OAI (pdf)
• Combinational-2 : Decoder, Mux, Tristate Inv (pdf)
• Combinational-3 : Standard Cell, Design Flow (pdf)

Sequential Circuit Design

Logic Level Sequential Circuit Design Overview

• Background (pdf)
• Sequential Timing (pdf)
• FSM Examples (pdf)

CMOS Level Sequential Circuit Design

• Sequential-1 : Modern Latch & Flipflop(pdf)
• Sequential-2 : Classical Latch & Flipflop(pdf)
• Sequential-3 : Latch & Flipflop Timing Constraints(pdf)
• Sequential-4 : Enable, Reset, Set (pdf)

Other MOS Logic Family Design

• Static-1 : Pseudo-nMOS, Transmission Gate (pdf)
• Static-2 : Skewed Inverters, Ratioed Logic (pdf)
• Dynamic-1 : Footed, Unfooted, Domino Logic (pdf)
• Dynamic-2 : Logical Effort of Dynamic Logic Gates (pdf)

Datapath Design

Ripple Carry Adder

• Logic Level Analysis (pdf)
• VHDL Implementations (pdf)
• CMOS Level Analysis (pdf)

Carry-Lookahead Adder

• Logic Level Analysis (pdf)
• VHDL Implementations (pdf)
• CMOS Level Analysis (pdf)

Carry Save Adder

• Logic Level Analysis (pdf)
• VHDL Implementations
• CMOS Level Analysis

Multiplier

• CMOS Level Analysis (pdf)
• Array Multiplier (pdf)
• Barrel Shifter (pdf)
• Other Multipliers (pdf)

Memory Array Subsystem Design

Logic Level Overview

• Background (pdf)
• DRAM Memory (pdf)
• For DRAM, SDRAM, DDR, see B. Jacob's lecture notes on umd
• For a simple computer architecture, see Tiny CPU example
• TinyCPU Architecutre Timing Diagrams

CMOS Level

• SRAM (pdf)
• DRAM (pdf)
• Cache

Logic Array Subsystem Design

Logic Level Overview
CMOS Level

Design Issues

Package

See also

• Understanding CMOS Design
• The necessities in Digital Design ‎
• The necessities in Computer Design ‎
• The necessities in Computer Architecture ‎
• The necessities in Computer Organization ‎
• Understanding Arithmetic Circuits ‎

• Understanding Low Power Design
• [Understanding Arithmetic Circuits]] ‎
• Understanding FPGA Design

go to [ Electrical_&_Computer_Engineering_Studies ]

External links

• R.J. Baker's Electric Tutorial
• S.M. Rubin's Electric User's Manual
• Open Circuit Design Software Magic/XCircuit/IRSIM/Netgen/Qrouter/Qflow/PCB