Computer Architecture Lab/Winter2006/LechnerWalterStadlerTrinkl/ThreeMicroDiscussion

Three microprocessor architectures:

1. Xilinx PicoBlaze (www.xilinx.com/picoblaze)

Xilinx Picoblaze is an 8-bit RISC microcontroller core optimized for the Spartan- and Virtex-FPGAs. PicoBlaze is delivered as free source level VHDL and can be used royalty-free. It was designed for low power consumption and low resource usage.

References

• PicoBlaze 8-bit Microcontroller Reference Design for FPGAs and CPLDs: http://www.xilinx.com/bvdocs/ipcenter/data_sheet/picoblaze_productbrief.pdf
• XAPP213: PicoBlaze™ 8-Bit Microcontroller for Virtex-E™ and Spartan-II/IIE™ Devices: http://www.xilinx.com/bvdocs/appnotes/xapp213.pdf

Memory

1K of instruction loaded during FPGA configuration and 64-byte internal RAM

I/O

256 input and 256 outport ports where each is 8-bit width. The individual output ports are addressed with the 8-bit address value. Data can be transferred from registers to ports or vice versa.

Registers

The processor support 16 general-purpose 8-bit registers.

Pipeline

The processor has no pipelining.

Interrupts

The interrupt vector is located at address 0xFF. When an interrupt occurs and interrupts are enabled the PC is set to this address. An interrupt pushes the program counter and the values of the Carry and Zero flags on the stack. They are restored by the RETURNI instruction.

Instruction set

The instruction set is grouped into the Program Control Group, Logical Group, Arithemtic Group, Shift and Rotate Group, Input/Output Group and Interrupt Group. In total the processor supports 59 instructions counting all variants, i.e. JUMP and JUMPZ are counted as different instructions. All instructions execute in 2 clock cycles and are of 16bit width. A list of all instructions is given below:

Programm control group

The programm control group includes instructions for branching (JUMP), calling subroutines (CALL) and returning from subroutines(RETURN) and interrupts(RETURNI). All instructions support an optional argument like Z(zero), NZ(not zero), C(carry) and NC(no carry) which make the instructions conditional. An example of the JUMP instruction is given below.

The JUMP instruction is conditional an can be skipped if either the CARRY or ZERO flag is set. The address space is fixed to 256 locations making the PC 8-bits wide.

JUMP instruction

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	0	0	C	C0	C1	0	1	a	a	a	a	a	a	a	a

Bit 12 ... 0 = UNCONDITIONAL, 1 = CONDITIONAL

Bit 11:10 ( 00 = If Zero, 01 = If not Zero, 10 = If Carry, 11 = If not carry )

Logical Group

The logical group includes boolean functions like AND(0001), OR(0010) and XOR(0011). In addtion a LOAD instruction is available which loads a register either with a constant or the value from another register. The instruction code is somewhat strange because the four bits which identify the instruction are either bit 12:15 or bit 0:3.

Bit 15:12	Bit 11:8	Bit 7:0
Code	sX (Destination Register)	KK (Constant )

AND, OR, XOR and LOAD using constant as source.

Bit 15:12	Bit 11:8	Bit 7:4
1100	sX (Destination Register)	sY (Source Register)

AND, OR, XOR and LOAD using other register are source.

Arithmetic Group

This group includes the arithmetic functions ADD(0100) and SUB(0110). Both instructions supports registers and constants. In addtion two variants ADDCY(0101) and SUBCY(0111) supporting the carry bit are available. The coding is the same as for the instruction of the logical group and is therefore not repeated here.

Shift and Rotate Group

The shift and rotate group includes four logical shift instructions SR0(110), SR1(111), SL0(110) and SL1(111). The shift either to the right (R) or to the left(L) where the value shifted in is either 0 or 1. In addition a Rotate Right RR(100) and Rotate Left (RL) instruction is available. Furthermore one arithmetic variant SLA(000) and SRA(000) and a special instruction SLX(100) and SRX(100) is present. The purpose of the SRX and SLX instruction is doubtful to the author because it shifts either to the right or to the left but uses the highest bit as shift value.

Bit 15:12	Bit 11:8	Bit 7:3	Bit 2:0
1101	sX (Destination Register)	00000(Left), 00001(Right)	XXX

Left/Right Shift and Rotate instructions

Input and Output Group

The INPUT(1010 for constant, 1011 for register) transfers data values from the external interface to the PicoBlaze core. The port address is in the range from 0 to 255. The address is either a constant or specified in a register.

Bit 15:12	Bit 11:8	Bit 7:0
1010	sX (Destination Register)	PP (Port ID)

Input instruction using constant as source

Bit 15:12	Bit 11:8	Bit 7:4	Bit 3:0
1011	sX (Destination Register)	sY (Source Register holding Port ID)	0000

Input instruction using register as source

The OUTPUT(1110) instruction has the same conding but the destination register is now the source register for the value written to the port.

2. Atmel ATMega8 (http://www.atmel.com)

References

• The ATMega8 is a 8-bit Microcontroller http://www.atmel.com/dyn/products/product_card.asp?part_id=2004

Memory

The ATMega8 has 8K Bytes of In-System Self-Programmable Flash, 512 Bytes EEPROM and 1K Byte Internal SRAM

I/O

The microcontroller has 23 programmable IO pins which can be used for various functions. These include for example a UART interface, a master/slave SPI interface, ADC converters and a 2 wire interface (I²C). It also does have external interrupt sources.

Registers

The microcontroller supports 32 x 8 general purpose working registers. Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing

Pipeline

The processor is single level pipelined, meaning that one instruction is beeing executed while another one is beeing fetched from the programm memory.

Instruction set

The instruction lenght varies from 16 to 32 Bit although most instructions are 16 Bit wide. It consists of 130 instructions which are grouped into the following sections: Arithmetic and logic instructions, Branch instructions, Data transfer instructions, Bit and Bit-test instructions and MCU control instructions. Most instructions are executed in a single cycle but it can take up to 5 cycles for certain instructions to execute. An example is given for each group.

Arithmetic and Logic instructions

The MUL instruction performs an unsigned multiplication with register Rd and register Rr. The 16 Bit output is saved to R1 (Highbyte) and R0 (Lowbyte);

Bit 15:12	Bit 11:8	Bit 7:4	Bit 3:0
1001	11rd	dddd	rrrr

Branch instructions

The RJMP instruction executes a relative jump to an address within PC - 2k + 1 and PC + 2k.

Bit 15:12	Bit 11:8	Bit 7:4	Bit 3:0
1100	kkkk	kkkk	kkkk

Data transfer instructions

The MOV instruction copies the content of one register into another.

Bit 15:12	Bit 11:8	Bit 7:4	Bit 3:0
0010	11rd	dddd	rrrr

Bit and Bit-test instructions

The SBI instruction sets s specifed bit in an I/O register. The instruction operates on the lower 32 I/O registers addresses 0-31.

Bit 15:12	Bit 11:8	Bit 7:4	Bit 3:0
1001	1010	AAAA	Abbb

MCU control instructions

This instruction sets the device into sleep mode for one cycle.

Bit 15:12	Bit 11:8	Bit 7:4	Bit 3:0
1001	0101	1000	1000

3. Alpha 21x64

The Alpha architecture is a 64 bit architecture, where all operations are performed on 64 bit wide registers. As all typical RISC processors Alpha constitutes a Load/Store architecture, i.e. data is loaded from memory into registers, then an operation is executed on these registers and finally results are written back on memory. Alpha processors were superscalar from the beginning.

References

• Alpha Architecture Handbook: http://www.phys.ufl.edu/~prescott/linux/alpha/dec3000-docs/alpha-arch-hdbk.ps.gz
  
• Wikipedia acrticle: http://en.wikipedia.org/wiki/DEC_Alpha

Memory

First Alpha processors had 8K instruction cache and 8K data cache. Later models (e.g. the EV6 versions) had 64K for I-cache and D-cache, respectively.

I/O

The EV4 processor had 290 I/O pins, the EV6 models had 389 pins and the latest Alpha processors that were shipped (EV7) came up with 1443 pins.

Registers

Each Alpha processor has 32 Integer registers and 32 registers for floating point operations.

Pipeline

The first Alpha processor (EV4) already contained two pipelines: one for integer instructions (7 stages) and one for floating point instructions (10 stages).

Instruction Set

The Alpha ISA is a 3-address archictecture, i.e. most operations have two source registers and one destination registers.

All Alpha instructions are 32 bit wide. There are four different instruction formats. All formats start with a 6 Bit long opcode. Because the register set counts 32 registers (either integer or floating point registers), registers can be addressed with five Bits.

Load and store Instructions

Memory access Instructions contain two registers (Ra and Rb) and a memory displacement. The displacement ist added to the second register (Rb) and the sum forms the memory address that is accessed with the operation.

E.g.: ldq Ra, disp(Rb)
Meaning: Load data from memory addess Rb+disp and store it into register Ra.

Bit 31:26	Bit 25:21	Bit 20:16	Bit 15:0
Opcode	Ra	Rb	Displacement

Conditional Branch Instructions

Branch instructions are needed to jump to a specified instruction of the program. The instruction tests the data contained in register Ra and modifies the program counter with the given displacement.

E.g.: beq Ra, label
Meaning: If Ra equals zero then goto the instruction that the label points on.

Bit 31:26	Bit 25:21	Bit 20:0
Opcode	Ra	Displacement

Operate Instructions

This group of instructions is basically formed by arithmetic and byte manipulation operations. Two source registers and one destination register can be specified. One source register can bit replaced by an eight bit immediate number that is directly encoded within the instruction word.

E.g.: addq Ra, Rb/immediate, Rc
Meaning: Add value of Ra and Rb (or immediate value) and write result into register Rc.

Bit 31:26	Bit 25:21	Bit 20:16	Bit 15:5	Bit 4:0
Opcode	Ra	Rb	Function	Rc

PALCode instructions

The abbreviation PAL stand for Priviledged Architecture Library. This instruction format used to specify extended processor functions. The 26 bit wide PALCode function field specifies the operation that should be executed.

Bit 31:26	Bit 25:0
Opcode	PALCode Function