Computer Architecture Lab/WS2008

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Project page for the course in winter 2008.

Contents

[edit] CD8 (Crazy Daisy Eight)

Martin Schoeberl Group 99

A two bit instruction 8-way VLIW design that will save the world.

[edit] Gruppe 0

Matthias Feurstein

[edit] IS1

Vergleich der Instruktionssets von:

  1. Z80
  2. Atmel AVR
  3. ARM7TDMI

Vergleich:


[edit] Gruppe 1

Julian Grahsl

Raffael Trimmal

Miodrag Pejic

Robert Najvirt

Vergleich der Instruktionssets von:

AVR 8-Bit

http://www.atmel.com/dyn/resources/prod_documents/doc0856.pdf

68000

http://www.freescale.com/files/archives/doc/ref_manual/M68000PRM.pdf
http://www.freescale.com/files/32bit/doc/ref_manual/MC68000UM.pdf

8080

Zu finden: Hier

[edit] Sweet 16 (Gruppe 2)

Franz-Josef Katzdobler, Daniel Reichhard, Stefan Resch, Matthias Wenzl

[edit] Instruction Set I

The discussion and the comparison of the instruction sets from

can be found here.

Documentation

[edit] Gruppe 3

Christian Pfeifhofer, Michael Wessner, Michael Zoech

[edit] Instruction Set 1

Comparison of the instruction sets of:

  1. PICMicro PIC16Cxxx
  2. DEC Alpha
  3. Intel 4004

[edit] Instruction Set 2

The instruction set of our processor:

[edit] Processor Documentation

The documentation of our processor is available in pdf format:

[edit] AUA (Another Useless Architecture)

  • Rottensteiner Stefan
  • Tauner Stefan
  • Wilhelm Jakob

[edit] Instruction Set Comparison

  • AVR32
  • Intel i960
  • SuperH

[edit] Our own CPU

A quite standard 16bit RISC implementation with 32 registers and probably a 4 stage pipeline (ex and mem combined).

AUA

[edit] Gruppe 5 (Project: MaQuelle)

[edit] Instruction Set I

  • Infineon TriCore
  • Freescale MPC7448 (PowerPC)
  • Motorola 68000

Comparison:

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