Computer Architecture Lab/FPGA Hello World Example
When one starts to use a new language or environment the first program written is usually the famous 'Hello World' example. What is the 'Hello World' program in hardware, in an FPGA? The smallest project that produces dynamic output is a blinking LED. We will show the steps for a blinking LED example using Altera's Quartus and the Cyclone board Cycore.
Design Flow 
All your design files (VHDL files) make up a project in Quartus. A Quartus II project is defined in Quartus II with just three files: projectname.qpf, projectname.qsf, and projectname.cdf (Close your Quartus II project before editing the files).
Create a New Project 
Start Quartus II and create a new project with:
- File -- New Project Wizard...
- Select a project directory and select a project name. The project name is usually the name of the top-level design entity. In our case hello_world (make sure to name the project this exactly, or you will have compilation problems).
- In the next dialog box the VHDL source files can be added to the project. As we have no VHDL files at the moment we will skip this step
- We have to select the target device. Choose family Cyclone and depending on your board either select EP1C6Q240C8 or EP1C12Q240C8 as device
- We leave the EDA tools settings blank
- Press Finish at the summary window
Device and Pin Options 
At the default setting the unused pins drive ground. However, some power pins from the EP1C12 are user pins in the EP1C6. The Cycore PCB can be used for both devices and therefore provides power on those pins. Driving them with ground (in the EP1C6) results in a short circuit between the ground driving pins and power. As the default settings in Quartus II for a device are dangerous we specify more details for our target device:
- Assignments -- Device to open the device properties
- Press the button Device & Pin Options...
- Important! At the tab Unused Pins select As input tri-stated.
- If you intend to configure a dspio board via the USB download utility (USBRunner) select .rbf at the tab Programming Files. In addition you have to uncheck Generate compressed bitstreams at the tab Configuration.
- The LVCMOS, selected in tab Voltage, is the better IO standard to interface e.g. SRAM devices
- Close the dialog box and the next with OK
The Hello World VHDL Example 
Add a VHDL file to the project with File -- New... and select VHDL File. Enter the following code and save the file with filename hello_world.
-- -- hello_world.vhd -- -- The 'Hello World' example for FPGA programming. -- -- Author: Martin Schoeberl (firstname.lastname@example.org) -- -- 2006-08-04 created -- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity hello_world is port ( clk : in std_logic; led : out std_logic ); end hello_world; architecture rtl of hello_world is constant CLK_FREQ : integer := 20000000; constant BLINK_FREQ : integer := 1; constant CNT_MAX : integer := CLK_FREQ/BLINK_FREQ/2-1; signal cnt : unsigned(24 downto 0); signal blink : std_logic; begin process(clk) begin if rising_edge(clk) then if cnt=CNT_MAX then cnt <= (others => '0'); blink <= not blink; else cnt <= cnt + 1; end if; end if; end process; led <= blink; end rtl;
The not yet famous VHDL 'Hello World' example
Compiling and Pin Assignment 
The analysis, synthesize, map, and place & route processes are all started with Processing -- Start Compilation. The compiler did not know that our PCB is already done, so the compiler assigned any pin numbers for the inputs and outputs.
If Full Compilation fails you may try to manually correct the toplevel entity.
However, the pin numbers are fixed for the board. We have to assign the pin numbers for our two ports clk and led. Open the pin assignment window with Assignments -- Pins. Our two ports are already listed in the All Pins window. Double click the field under Location and select the pin number. Enter following assignments:
clk PIN_152 led PIN_166
With the correct pin assignment restart the compilation with Processing -- Start Compilation (or use the play button) and check the correct assignment in the compilation report under Fitter -- Pin-Out-File. The clk pin should be located at 152 and led at 166; all unused pins should be listed as RESERVED_INPUT.
FPGA Configuration 
Downloading your hardware project into the FPGA is called configuration. There are several ways an FPGA can be configured. Here we describe configuration via JTAG.
This section describes configuration via ByteBlasterMV connected to the printer port.
- Connect your ByteBlasterMV to the printer port of the PC
- Connect the other end to the JTAF header on the FPGA board. The red wire should point to pin 1 (written on the PCB)
- Start the programmer with Tools -- Programmer
- Press the button Auto Detect and the programmer window should list two devices: an EPM2064A/7064AE and an EP1C6 or EP1C12
- Double click for the filename of the EP1C6/12 device and select hello_world.sof. Leave the file blank for the EPM2064A/7064AE device
- Select the checkbox under Program/Configure for the EP1C6/12 and press the Start button to configure the FPGA
The LED should now blink!
The dspio board can (also) be configured via the USB connection. In that case a short cable connects the JTAG header from the Cycore board with the JTAG header of the dspio board. The command line tool USBRunner needs a raw binary file (hello_world.rbf) for the FPGA configuration.
We already told Quartus to generate this file. But the raw binary file can also be generated manually in the following manner using Quartus (we don't need to do this any more):
- Start the Convert Programming Files Generator using File -- Convert Programming Files
- At Programming File Type select Raw Binary File (.rbf)
- At File Name change the name to the name of your project (in example hello_world.rbf)
- At Input files to convert click on SOF Data. Now the Add File button changes and you can select the .sof file of your project (hello_world.sof).
- Press the Generate button to generate the file.
Now you can download your project using the USBRunner. Open a command line box, select the path of your project and type USBRunner hello_world.rbf and press enter.
The LED should now blink!
Further Information 
- The VHDL source files and the project files do not have to be in the same directory. Keeping them in separate directories is a better organization and simplifies reuse
- Use relative paths wherever possible to enable project sharing
- In general choose the entity name as filename. However, with different files (and names) for different versions of an entity a project can be easily configured just with different Quartus II projects
Quartus File Types 
The most important file types used by Quartus:
- Quartus II Project File. Contains almost no information.
- Quartus II Settings File defines the project. VHDL files that make up your project are listed. Constraints such as pin assignments and timing constraints set here.
- Chain Description File. This file stores device name, device order, and programming file name information for the programmer.
- Tool Command Language. Can be used in Quartus to automate parts of the design flow (e.g. pin assignment).
- SRAM Output File. Configuration for Altera devices. Used by the Quartus programmer or by quartus_pgm. Can be converted to various (or too many) different format. Some are listed below.
- Raw Binary File. Configuration for Altera devices. Used by the USB download utility (USBRunner) to configure the dspio board via the USB connection.
- Quarts II Web Edition - VHDL synthesis, place and route for Altera FPGAs
- Jam STAPL Byte-Code Player - FPGA configuration in batch mode (jbi32.exe)
- Cycore Schematic - The board used in this example
- DSPIO board -- The home of the dspio extension (schematic and USBrunner)
- hello_world.pdf -- This document as .pdf