MIssonPoSsible architecture:
We are using parts of the MIPS instruction set and architecture to archive a some what conmpatibility.
In sum the processor possesses 25 instructions.
The architecture uses 32x32 bit registers, of which 29 are general purpose registers status register, zero register and a special register.
(+ 32 bit program counter.)
The following table contains all status flags used for arithmetical operations
and branch decisions:
Abbrev. Description
N Negative
O Overflow
Z Zero
R Random Flag
The Overflow bit is set after multiplication operations arithmetic operations (MUL, MULU, ADD, SUB, shift operations) if the results needs more than 32bit. For additions it works as carry bit. The Zero bit is set if the result of the last operation was zero. The Negative flag is set, when the last operation was a signed-numbers operations and the result was negative. The random bit is randomly set after each clock cylce.
The following are the six formats used for the core instruction set:
Type
-31- format (bits) -0-
Arithmetical
opcode (6)
rs (5)
rt (5)
rd (5)
reserved (11)
Load/Store
opcode (6)
rs (5)
rt (5)
reserved (16)
Branch
opcode (6)
reserved(10)
immediate (16)
Shift
opcode (6)
reserved (5)
rt (5)
rd (5)
immediate (5)
reserved (6)
Jump
opcode (6)
rs (5)
reserved (21)
NOOP
111111
reserved (21)
Simplified:
Type
-31- format (bits) -0-
R
opcode (6)
rs (5)
rt (5)
rd (5)
immediate (5)
reserved (6)
I
opcode (6)
rs (5)
rt (5)
immediate (16)
Supported operations:
ADD -- Add
Description: Adds two registers and stores the result in a register
Operation: $d = $s + $t; advance_pc (4);
Syntax: add $d, $s, $t
Encoding: 1111 00ss ssst tttt dddd dxxx xxxx xxxx
ADDU -- Add unsigned
Description: Adds two registers and stores the result in a register
Operation: $d = $s + $t; advance_pc (4);
Syntax: addu $d, $s, $t
Encoding: 0011 00ss ssst tttt dddd dxxx xxxx xxxx
AND -- Bitwise and
Description: Bitwise ands two registers and stores the result in a register
Operation: $d = $s & $t; advance_pc (4);
Syntax: and $d, $s, $t
Encoding: 1010 00ss ssst tttt dddd dxxx xxxx xxxx
BR -- Unconditional Branch
Description: Jumps to relative address
Operation: advance_pc (offset << 2));
Syntax: br offset
Encoding: 0100 01xx xxxx xxxx iiii iiii iiii iiii
BZS -- Branch on zero set
Description: Branches if zero flag in status register is set
Operation: if zero == TRUE advance_pc (offset << 2)); else advance_pc (4);
Syntax: bzs offset
Encoding: 1000 10xx xxxx xxxx iiii iiii iiii iiii
BZC -- Branch on zero clear
Description: Branches if zero flag in status register is cleared
Operation: if zero == FALSE advance_pc (offset << 2)); else advance_pc (4);
Syntax: bzc offset
Encoding: 1000 10xx xxxx xxxx iiii iiii iiii iiii
BOS -- Branch on overflow set
Description: Branches if overflow flag in status register is set
Operation: if overflow == TRUE advance_pc (offset << 2)); else advance_pc (4);
Syntax: bos offset
Encoding: 1000 01xx xxxx xxxx iiii iiii iiii iiii
BNS -- Branch on negative set
Description: Branches if negative flag in status register is set
Operation: if negative == TRUE advance_pc (offset << 2)); else advance_pc (4);
Syntax: bns offset
Encoding: 0111 01xx xxxx xxxx iiii iiii iiii iiii
BNC -- Branch on negative clear
Description: Branches if negative flag in status register is cleared
Operation: if negative == FLASE advance_pc (offset << 2)); else advance_pc (4);
Syntax: bnc offset
Encoding: 0111 01xx xxxx xxxx iiii iiii iiii iiii
BOR -- Branch on random
Description: Branches if Random Flag is set
Operation: if lsb(random reg.) == TRUE advance_pc (offset << 2)); else advance_pc (4);
Syntax: bor offset
Encoding: 0110 11xx xxxx xxxx iiii iiii iiii iiii
JR -- Jump register
Description: Jump to the address contained in register $s
Operation: PC = nPC; nPC = $s;
Syntax: jr $s
Encoding: 0110 00ss sssx xxxx xxxx xxxx xxxx xxxx
LLI -- Load lower immediate
Description: The 16bit immediate value is stored in the lower word of the destiny register. The higher word is unchanged. Operation: $t = ($t & 0xFF00)+imm; advance_pc (4);
Syntax: lli $t, imm
Encoding: 0101 00xx xxxt tttt iiii iiii iiii iiii
LW -- Load word
Description: A word is loaded into a register from the specified address.
Operation: $d = MEM[$s]; advance_pc (4);
Syntax: lw $d, $s
Encoding: 0100 10ss sss0 0000 dddd dxxx xxxx xxxx
NOOP -- no operation
Description: Performs no operation.
Operation: advance_pc (4);
Syntax: noop
Encoding: 1111 1100 0000 0000 0000 0000 0000 0000
OR -- Bitwise or
Description: Bitwise logical ors two registers and stores the result in a register
Operation: $d = $s | $t; advance_pc (4);
Syntax: or $d, $s, $t
Encoding: 1001 11ss ssst tttt dddd dxxx xxxx xxxx
SLL -- Shift left logical
Description: Shifts a register value left by the shift amount listed
in the instruction and places the result in a third register. Zeroes are shifted in.
Operation: $d = $t << i; advance_pc (4);
Syntax: sll $d, $t, i
Encoding: 1100 11xx xxxt tttt dddd diii iixx xxxx
SLLV -- Shift left logical variable
Description: Shifts a register value left by the value in a second
register and places the result in a third register. Zeroes are shifted in.
Operation: $d = $t << $s; advance_pc (4);
Syntax: sllv $d, $t, $s
Encoding: 1100 00ss ssst tttt dddd dxxx xxxx xxxx
SRA -- Shift right arithmetic
Description: Shifts a register value right by the shift amount
and places the value in the destination register. The sign bit is shifted in.
Operation: $d = $t >> i; advance_pc (4);
Syntax: sra $d, $t, i
Encoding: 1011 10xx xxxt tttt dddd diii iixx xxxx
SRL -- Shift right logical
Description: Shifts a register value right by the shift amount
and places the value in the destination register. Zeroes are shifted in.
Operation: $d = $t >> i; advance_pc (4);
Syntax: srl $d, $t, i
Encoding: 1011 01xx xxxt tttt dddd diii iixx xxxx
SRLV -- Shift right logical variable
Description: Shifts a register value right by the amount
specified in $s and places the value in the destination register. Zeroes are shifted in.
Operation: $d = $t >> $s; advance_pc (4);
Syntax: srlv $d, $t, $s
Encoding: 1010 11ss ssst tttt dddd dxxx xxxx xxxx
SUB -- Subtract
Description: Subtracts two registers and stores the result in a register
Operation: $d = $s - $t; advance_pc (4);
Syntax: sub $d, $s, $t
Encoding: 1110 10ss ssst tttt dddd dxxx xxxx xxxx
SUBU -- Subtract unsigned
Description: Subtracts two registers and stores the result in a register
Operation: $d = $s - $t; advance_pc (4);
Syntax: subu $d, $s, $t
Encoding: 0010 10ss ssst tttt dddd dxxx xxxx xxxx
SW -- Store word
Description: The contents of $t is stored at the specified address.
Operation: MEM[$s] = $t; advance_pc (4);
Syntax: sw $s, $t
Encoding: 0011 11ss ssst tttt xxxx xxxx xxxx xxxx
XOR -- Bitwise exclusive or
Description: Exclusive ors two registers and stores the result in a register
Operation: $d = $s ^ $t; advance_pc (4);
Syntax: xor $d, $s, $t
Encoding: 1001 00ss ssst tttt dddd dxxx xxxx xxxx
The opcodes have a hamming distance of 2.
opcode
-31- instruction -0-
111111
NOOP
111100
ADD
001100
ADDU
111010
SUB
001010
SUBU
110110
SRL
110101
SRLV
110011
SLL
110000
SLLV
101110
SRA
101101
SRL
101011
SRLV
101000
AND
100111
OR
100100
XOR
010001
BR
010111
BNC
100010
BZS
100001
BOS
011101
BNS
011110
BZC
011011
BOR
011000
JR
010100
LLI
010010
LW
001111
SW
register (register-absolute addressing for direct jumps)
immediate (immediate-relative addressing for branches)
Samples Instruction Set 2
Hamming-Tool
http://www.ee.unb.ca/cgi-bin/tervo/hamming.pl